1. Field of the Invention
This invention relates generally to an electrically erasable programmable read only memory (EEPROM) device. More particularly, the invention relates to programming control techniques adaptable for use with the nonvolatile memory devices.
2. Description of Related Art
EEPROM memory cells are generally designed to employ metal oxide semiconductor (MOS) transistors with stacked structures of a floating gate and a control gate. In flash EEPROM memories of the so-called NAND type, a plurality of memory cells are connected in series together to make up a NAND cell unit. The NAND-type flash memories store data in a nonvolatile way while regarding a threshold voltage-increased state due to injection of electrons into the floating gate of a memory cell as a data bit of logic “0” (write or program state) and letting a threshold voltage-decreased state due to release or discharge of the electrons on the floating gate be a data bit of logic “1” (erase state). One exemplary threshold voltage distribution pattern of the data is shown in FIG. 4. A data writing or “programming” operation is performed by controlling via a bit line the channel potential of a NAND cell unit in a data-dependent way and then applying a program voltage to a selected word line. An ordinary programming operation is performed as follows.
When the program data is a logic “0,” apply a voltage of 0 volt (V) to a corresponding bit line, thereby precharging the channel of a NAND cell unit to 0V through a select gate transistor of the NAND cell unit. When the program data is a logic “1” (program inhibited), apply Vdd (V) to a corresponding bit line, then transfer it to a NAND cell unit's channel through a select transistor. In this case, the channel is precharged to Vdd−Vt (where, Vt is a threshold voltage of the select transistor) to be floating state with a potential level Vdd−Vt. Then, give a potentially raised or “boosted” program voltage Vpgm to a selected word line. Based on the program voltage application, at the cell with logic “0” data given thereto, a sufficiently high voltage is applied between the gloating gate and the channel. As a result, its threshold voltage gets higher due to electron injection from the channel into the floating gate. In the cell with “1” data given thereto, the floating NAND cell unit channel is boosted by the program voltage Vpgm applied to the selected word line and the pass voltage Vpass applied to non-selected word lines. Therefore, since no electron injection into the floating gate takes place, the “1” data cell stays unchanged.
In a practical data program operation, as shown in FIG. 5, applying a program pulse voltage and reading data for verification—say, verify-read—are recurrently performed while gradually shifting a program pulse voltage value in a stepwise fashion, thereby forcing the data “0” to finally fall within a prespecified range of threshold-voltage distribution.
In the program-verify operation, a verify read voltage Vpv is applied to the selected word line. When the threshold voltage of the selected cell is over Vpv by the just before program pulse application, the programming operation for the selected cell is ended. When the threshold voltage of the selected cell is lower than Vpv, the programming operation for the selected cell is continued.
Such the programming control for the respective selected memory cells is performed in a page buffer. The page buffer is configured to have a sense amplifier function and a data latch function that is to temporarily hold read data and program data.
Program data of one page are loaded in the page buffer at the beginning of the program operation. “0” and “1” loaded data correspond to “0” and “1” programming, respectively. When a “0” programmed cell becomes to have a predetermined threshold voltage, a logic “H” data (i.e., “1” data) is latched in the page buffer as a result of bit line sensing in the program verify-read operation. By contrast, with respect to a “1” programmed cell, logic “H” data (i.e., “1” data) is held in the page buffer in spite of the result of bit line sensing. Therefore, by repeating the program pulse application and the verify-read until when all data bits of the page buffer become logic “1”s, it is able to program desirable data into all memory cells within a selected page.
Data erase is done in units of NAND cell blocks. Each NAND cell block has a plurality of NAND cell units in a direction along word lines—say, wordline direction. More specifically, all of the memory cells in the NAND cell block are erased at a time. This is called as “all-at-a-time” or “all-at-once” erase in the flash memory device art. To perform such all-at-once erase for a selected NAND cell block, let all the word lines associated with this cell block be set at 0V, and apply a boosted erase voltage Vera to a semiconductor well region in which the NAND cell block is formed and also to the channel regions of memory cell transistors therein. With such voltage application, every memory cell experiences release of electrons on its floating gate toward the channel thereof and thus is set in the data “1” storage state with a lowered threshold voltage. In other words, all the cells are “erased” simultaneously.
In this data erase session also, performing a verify-read operation for checking the erase state makes it possible to force the threshold-voltage distribution to fall within a predetermined range.
In the EEPROM of the type stated above, the threshold voltage used as a reference level for deciding “0” data in a program verify-read is set at a lower limit value Vpv of the threshold voltage distribution of “0” data, as shown in FIG. 4. In most cases, no attempts are made to verify an upper limit value of the data “0” threshold voltage distribution. However, “0” programmed memory cells are accidentally programmed to have an unintentionally high threshold voltage beyond the expected threshold voltage distribution. This is called as an over-program or an over-write.
Once such an over-program occurs, it becomes impossible to precisely read out a cell data in such a NAND cell unit that includes an over-programmed cell. The reason is as follows. In the data read operation, a read voltage Vrr (for example, 0V) is applied to a selected word line, and a pass voltage Vread is applied to non-selected word lines. The pass voltage Vread is predetermined as to be able to turn-on the non-selected memory cell regardless of whether the data held therein is “0” or “1”. If an over-programmed cell is included in the non-selected cells, the cell current will be cut-off or limited at the over-programmed cell. As a result, “0” data will be read out regardless of whether the data of the selected cell is “0” or “1”.
Additionally, “1” data-programmed memory cells (i.e., those expected to store logic “1” data) in the memory cells along a selected word line with the program voltage Vpgm applied thereto become in a weak “0” program mode. As a result, in “1” data-programmed memory cells, such erratic programs or erratic writes may occur that threshold voltages thereof become unusually higher than the upper limit, Vev, of “1” data threshold voltage distribution. As a result of such the erratic programs, some of the memory cells to be held in a “1” data state may become erroneously programmed states with a threshold voltage lager than the read voltage Vrr as shown in FIG. 4, read data of which are determined as “0”. Even when the cells that must store logic “1” data improperly behave to store “0” data, prior known program-verify schemes are incapable of detecting this kind of faults in any way.
Usually, a memory system has an error checking and correcting (ECC) circuit, the capability of which is designed in consideration of frequency of the above-described over-program and error program occurrence. Therefore, in a normal data read operation, even if there are error bits due to the over-program or erroneous program, correct data corrected by the ECC circuit may be read out.
However, when considering such a copy operation as to copy a certain page data of an EEPROM to another page thereof, above-described error bits occurred in a program operation becomes a problem to be solved, because of that a page data including error bits are programmed to another page as it is. In order to solve such the problem, it is required to check the read out data and correct it when it includes error bits by the ECC circuit. However, the ECC processing takes time, even if only data check is performed, thereby preventing the speed-up of the page copy operation.
In order to perform a reliable copy operation without employing an ECC circuit, it is necessary to detect the above-described over-programmed cells and erroneously programmed cells in the programming sequence, and inform the resultant to the memory chip controller when such the cells are detected. Methods of over-program verify and erratic program verify for such the purpose have already been proposed at present day, one of which is disclosed, for example, in Published Unexamined Japanese Patent Application No. 2000-100178 (“JP-A-2000-100178”). As taught thereby, over-program verify operation is performed after the ordinary program operation is ended. In details, the verify-read operation is performed by applying a predetermined pass voltage to a selected word line to determine whether an over-program is present or not. However, even if such the over-program verify operation is added to the program sequence, the reliability of programming is not yet sufficient for achieving a high speed copy operation without use of ECC circuitry.
In regard to erratic programs, the above-identified Japanese document suggests that it may be performed after the ordinary program operation is ended. Erroneously programmed cells are detected by performing two read operations in which different voltages are applied to a selected word line. By such the two read operations, whether a selected cell's threshold is higher than the ordinary read voltage (i.e., 0V) or not, and whether it is lower than the lower limit of “0” data threshold distribution or not may be detected. Other proposals for the erratic program verify are the same as this. However, in such the proposed verify method, supposing that a cell threshold of which is nearly equal to 0V is verified as it was normally programmed (“Pass”), it easily becomes erroneously programmed state due to some variation causes after the program sequence.